The silicon bipolar transistor has been the device of choice for high power applications in motor drive circuits, appliance controls, robotics and lighting ballasts. This is because bipolar transistors can be designed to handle relatively large current densities in the range of 40-50 A/cm.sup.2 and support relatively high blocking voltages in the range of 500-1000 V.
Despite the attractive power ratings achieved by bipolar transistors, there exist several fundamental drawbacks to their suitability for all high power applications. First of all, bipolar transistors are current controlled devices which require relatively large base currents, typically one fifth to one tenth of the collector current, to maintain the transistor in an operating mode. Proportionally larger base currents can be expected for applications which also require high speed turn-off. Because of the large base current demands, the base drive circuitry for controlling turn-on and turn-off is relatively complex and expensive. Bipolar transistors are also vulnerable to premature breakdown if a high current and high voltage are simultaneously applied to the device, as commonly required in inductive power circuit applications. Furthermore, it is relatively difficult to operate bipolar transistors in parallel because current diversion to a single transistor typically occurs at high temperatures, making emitter ballasting schemes necessary.
The silicon power MOSFET was developed to address this base drive problem. In a power MOSFET, the gate electrode provides turn-on and turn-off control upon the application of an appropriate gate bias. For example, turn-on in an N-type enhancement MOSFET occurs when a conductive N-type inversion layer is formed in the P-type channel region in response to the application of a positive gate bias. The inversion layer electrically connects the N-type source and drain regions and allows for majority carrier conduction therebetween.
The power MOSFET's gate electrode is separated from the channel region by an intervening insulating layer, typically silicon dioxide. Because the gate is insulated from the channel region, little if any gate current is required to maintain the MOSFET in a conductive state or to switch the MOSFET from an on-state to an off-state or vice-versa. The gate current is kept small during switching because the gate forms a capacitor with the MOSFET's channel region. Thus, only charging and discharging current ("displacement current") is required during switching. Because of the high input impedance associated with the insulated-gate electrode, minimal current demands are placed on the gate and the gate drive circuitry can be easily implemented. Moreover, because current conduction in the MOSFET occurs through majority carrier transport only, the delay associated with the recombination and storage of excess minority carriers is not present. Accordingly, the switching speed of power MOSFETs can be made orders of magnitude faster than that of bipolar transistors. Unlike bipolar transistors, power MOSFETs can be designed to withstand high current densities and the application of high voltages for relatively long durations, without encountering the destructive failure mechanism known as "second breakdown". Power MOSFETs can also be easily paralleled, because the forward voltage drop of power MOSFETs increases with increasing temperature, thereby promoting an even current distribution in parallel connected devices.
In view of these desirable characteristics, many variations of power MOSFETs have been designed. As illustrated by FIG. 1, one type of MOSFET is a vertical MOSFET having a trench gate. In this vertical MOSFET, a relatively lightly doped N-type drift region 3 is formed on a relatively highly doped N-type substrate 1. In addition, a P-type body region 5 is provided in the drift region 3 and an N-type source region 7 is provided in the body region 5. A trench "t" is also provided at a face of the drift region 3. The trench "t" extends through the source region 7 and through the body region 5, as illustrated. An insulated gate electrode is also provided in the trench. The insulated gate electrode includes a gate electrode 11 which is surrounded by electrically insulating regions 9 and 13 (e.g., SiO.sub.2). A patterned phosphosilica glass (PSG) layer 15 is also formed on the insulated gate electrode. The patterned PSG layer 15 exposes a portion of the source region 7 and body region 5. A layer of metallization is also formed on the exposed portions of the source region 7 and body region 5. This layer of metallization comprises a first electrode 17.
As will be understood by those skilled in the art, the body region 5 may be formed by initially forming a relatively lightly doped P-type well region and then increasing the doping concentration of the well region in the vicinity of the first electrode 17 using an ion implantation step. This increase in doping concentration in the body region 5 facilitates the formation of an ohmic contact with the first electrode 17 and improves the breakdown voltage of the vertical MOSFET. Unfortunately, the increase in doping concentration in the vicinity of the first electrode 17 may also influence the doping concentration of the body region 5 in the vicinity of the sidewall of the trench "t" if the spacing between adjacent trenches (in a multicelled device) is decreased to achieve increased integration densities or the ion implantation step is misaligned. As will be understood by those skilled in the art, any increase in the doping concentration of the body region 5 in the vicinity of the trench may increase the MOSFETs threshold voltage and deteriorate the MOSFETs turn-on and other electrical characteristics.
Thus, notwithstanding the above attempts to develop power MOSFETs and MOSFET-controlled semiconductor devices, there still continues to be a need for improved semiconductor devices for power applications.